This invention relates to semiconductor memories, and more particularly to metal-oxide-silicon dynamic storage random access memories. For convenience, the latter are hereinafter referred to simply as RAM's.
Basically, a typical RAM contains a plurality of spaced apart charge storage regions which are interconnected via respective transfer gates to a plurality of bit lines. The storage regions, the transfer gates, and the bit lines are all fabricated on one surface of a semiconductor chip. To write data into and read data from a particular storage area, the corresponding transfer gate is selectively enabled.
Over the past several years, the number of storage regions per RAM chip has continually increased. Early RAM chips contained only 64 storage areas; whereas present day RAM chips contain up to 65K storage areas. Several factors have contributed to this achievement. However, a major factor has been the development of techniques for decreasing the dimensions of the various RAM components.
One phenomenon, however, which limits how far those dimensions can be shrunk is called "narrow channel width effect". From a functional point of view, the "narrow channel width effect" shows up as an increase in the threshold voltage level of the transfer devices as their channel width is decreased. This phenomenon begins to occur when the channel width is about 3-4 microns for reasonable substrate concentrations, such as 10.sup.15 for example. Then as the channel width is decreased further, the threshold voltage increases at an exponential rate.
Mathematically, the threshold voltage may be expressed as V.sub.t =V.sub.to +.gamma.(.sqroot.V.sub.BS +2.phi..sub.F -.sqroot.2.phi..sub.F). In this equation, .gamma. is a parameter which increases exponentially as the channel width decreases below about 3-4 microns. The other terms are relatively constant and are defined as follows: V.sub.to equals threshold voltage with zero substrate bias, V.sub.BS equals substrate to source bias, and .phi..sub.F equals the Fermi level.
Clearly, an upper limit for V.sub.t exists beyond which the memory simply won't operate. As V.sub.t increases, the amount of charge that can be written into a storage region decreases. And eventually, the amount of charge becomes so small that it cannot be detected. A problem then is how to narrow the width of the channel beyond 3-4 microns in the memory's transfer devices and at the same time not raise .gamma..
Another phenomenon which limits how far the RAM's dimensions can be shrunk is parasitic capacitive coupling from the bit lines to the substrate. This capacitance is alway present. It is due, for example, to a P-N junction that is formed between diffused N+ bit line in a P-type substrate. Some memories have polysilicon or metal bit lines that lie on insulating layers above the substrate, which lowers the bit line to substrate coupling capacitance, but does not eliminate it.
From an A-C circuits viewpoint, the bit line capacitance is in series with two storage capacitances that purposely exist. One of the storage capacitances is formed by the interface between the substrate and storage regions. And the other storage capacitance is formed by the interface between the storage region and overlying field plate. These storage capacitors are formed to hold charge (which represents either a "1" or a "1") in the memory.
However, due to the parasitic bit line capacitance, the information in the storage regions is altered as the bit lines are precharged prior to the reading of a cell. For example, suppose that 0 volts is initially stored in the cell, and that the bit lines are subsequently precharged from 0 volts to 5 volts. This 5 volt rise on the bit lines is divided among the above described three capacitors; which in turn changes the voltage that is stored in the cell to some higher level. Consequently, the originally stored 0 volts more difficult to detect.
One way in which this problem has been handled in the smaller memories of the past was to provide an external pin on each memory chip that connects to the chip substrate. Then, in a operating system, that pin was connected to an external voltage source which was insensitive to voltage changes on the bit lines. However, modern memory chips have a large number of memory cells, and consequently they require a large number of pins for receiving signals to address the cells. Thus, present day 65K memories include no separate pin for biasing the substrate from an external supply. Instead, the substrate is biased with a voltage that is created internal to the chip which will fluxuate as described above when the bit lines are precharged.
Therefore, a primary object of the invention is to provide an improved RAM.
Another object of the invention is to provide a RAM having transfer devices of less than 3-4 micron width that exhibit greatly reduced narrow channel width effect.
Still another object of the invention is to provide a RAM having a substrate which is biased by an on chip voltage source and which is insensitive to voltage changes on the bit lines due to capacitive coupling.